1. Field of the Invention
Embodiments of the present invention relate to the field of electronic circuitry. More specifically, embodiments of the present invention relate to memory where dual port operation can be emulated for applications operating according to multiple clock domains using a single port memory.
2. Related Art
Random access memory cells or RAMs have become increasingly more popular due in part to the attractive costs of these devices. Many conventional RAM cells are ordinarily only addressable from a single port. In such a memory apparatus, the input of a binary address causes a single select line or coincidence of two select lines, such as a row select line and a column select line, to cause the addressed cell to be selected. Upon selection of a cell, data may then be sensed from or written into the selected storage cell on one or two bit sense lines. Alternatively, in some RAM cells, a single selection line causes the particular cell to be selected, and other selection circuitry activated by the same address causes the bit-sense lines to be selected. However, there are generally no options for addressing, sensing, and writing. The same selection lines and the same bit sense lines are always utilized to access, write to, and sense a particular location. Consequently, a single port RAM memory device cannot be simultaneously addressed and accessed from separate sources, thus, limiting access speed at which the RAM memory may be accessed.
However, certain applications require higher memory access speeds than what a single port RAM memory device can provide. Examples of such high speed applications may be graphic related memory systems such as those used in computer display systems, data transfer and buffering devices used in high speed communications systems, and memory systems used in communication with arithmetic logic units. For such applications, multi-ported random access memory devices have been developed to provide higher access speeds and increased accessibility to the memory contents of the random access memory unit. One example of a multi-ported memory device is a dual-ported RAM cell accessible simultaneously by two independent entities. In digital integrated circuits (ICs), this implies a dual-ported memory cell that can be accessed at the same time through two different ports. Each port utilizes independent sets of addresses and control lines to access the memory array using more than one clock (referred to hereinafter as “multiple clock domains”) to synchronize the data from the address and control lines.
FIG. 1 depicts a block diagram of dual-ported memory. The device 100 depicted in FIG. 1, includes a dual-ported memory 130 with two ports (110, 120). Therefore, one entity can read and/or write data to dual-ported memory 130 using port 110 while another entity may simultaneously read and/or write data to dual-ported memory 130 using port 120. Each port supports a respective address bus (112, 122) and respective buses (114, 124) for data input and output (as well as port clock lines (116, 126) for controlling the synchronization of reading and/or writing data to and/or from the port data buses (114, 124). Since, device 100 has two clock lines (116, 126) for synchronizing data input and/or output, device 100 can support “multiple clock domains,” enabling the processing of large amounts of data very quickly and efficiently.
Although the dual-ported memory 100 provides an effective solution for dual-port functionality, it results in large circuit designs and high development costs. For each new generation of fabrication process technology, a new dual port cell must be designed and tested, leading to additional development costs. For the same density, a dual-ported memory 100 is approximately twice the size of a single-ported memory. As performance requirements rise, more advanced technology may be required to implement a dual-ported memory than to implement a single-ported memory, rendering the conventional dual-ported memory less attractive.
FIG. 2 depicts a block diagram of another type of dual-ported memory. As depicted in FIG. 2, the dual-ported memory 200 has a port clock domain 212, which is associated with a clock signal that is received on port clock line 224, and a memory clock domain 214, which is associated with a clock signal that is communicated on clock line 226. A clock domain boundary 262 separates the port clock domain 212 from the memory clock domain 214.
Data is received by the dual-ported memory 200 at the port data bus 222. The clock signal received on port clock line 224 is used for synchronizing data received on port data bus 222. The data that is received on port data bus 222 crosses the clock domain boundary 262 through a data first-in-first-out (FIFO) 230, which is used to synchronize the data received on port address bus 222 with the memory clock domain 214.
The data is communicated from the data FIFO 230 to a memory controller 240 along bus 232. The address logic 242 of memory controller 240 generates an address that the data may be stored at in the single clock domain memory 250. Memory controller 240 communicates the data to the single clock domain memory 250, along with the generated address, and a clock signal along the respective buses (244, 246) and control line (226). Single clock domain memory 250 stores the data at the address that address logic 242 generated.
Although device 200 is size efficient it can only be used for uni-directional data flow and is most suitable for sequential data processing.